1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly, to a semiconductor memory having an array of memory cell units each constituted by cascade-connecting a plurality of memory cells with each other.
2. Description of the Related Art
There is conventionally known a DRAM which has a memory cell array arranged by a scheme in which NAND memory cell units are formed by cascade-connecting a plurality of memory cells with each other, and the plurality of memory cell units are connected to a bit line. In this cell array scheme, the number of bit line contacts is smaller than that in a scheme in which memory cells are respectively connected to bit lines. For this reason, a cell area can be advantageously decreased.
In this NAND cell array scheme, in order to read out data from a memory cell far away from a bit line, the data of the memory cell closer to the bit line than the above memory cell is broken. For this reason, registers for temporarily storing the data of the memory cell units and writing the data again are required (for example, IEEE ISSCC DIGEST OF TECHNICAL PAPERS, VOL. 34, p. 106, TAM 6.2, 1991).
FIG. 1 shows a semiconductor memory using a conventional NAND cell array scheme. Referring to FIG. 1, reference numeral 1 denotes a NAND array constituted by cascade-connecting, e.g., four memory cells M with each other; 2, a register cell array constituted by four memory cells RM corresponding to the memory cells M; 3, sense amplifiers; 4, a row decoder; and 5, a register row decoder.
In this memory, in order to read the data of one memory cell unit and write the data again, the following operations are performed. That is, a word line WL0 is activated, the data of a memory cell M0 is sensed, and bit lines BL are charged/discharged. In addition, a register cell word line RWL0 is activated, the data of the memory cell M0 is transferred to a register cell RM0, and the register cell word line RWL0 is de-activated, thereby securing the data of the register cell RM0. For this reason, in order to read out 1-bit data from a memory cell M and transfer it to a register RM, a word line WL is activated once, a register cell word line RWL is activated once and de-activated once. In addition, in order to write 1-bit data in the memory cell again, the register cell word line RWL is activated once and de-activated once, and the word line WL is de-activated once.
Therefore, in a cell in which one unit is constituted by four bits, as shown in FIG. 2, four word lines are activated once and de-activated once, and four register word lines are activated twice and de-activated twice (although a register word line RWL3 may be activated once and de-activated once), and each bit line is charged/discharged times corresponding to the number of times of activation of the register word lines. For this reason, currents required for charging/discharging the word lines, the register word lines, and the bit lines are considerably increased, and a time required for accessing a memory cell is disadvantageously prolonged.